High-speed, fixed-latency serial links with Xilinx FPGAs

IMR OpenIR

	High-speed, fixed-latency serial links with Xilinx FPGAs
其他题名	High-speed, fixed-latency serial links with Xilinx FPGAs
	Liu Xue 1; Deng Qingxu 1; Hou Boning 1; Wang Zeke 2
	2014
发表期刊	JOURNAL OF ZHEJIANG UNIVERSITY-SCIENCE C-COMPUTERS & ELECTRONICS
ISSN	1869-1951
卷号	15 期号:2 页码:153-160
摘要	High-speed, fixed-latency serial links find application in distributed data acquisition and control systems, such as the timing trigger and control (TTC) system for high energy physics experiments. However, most high-speed serial transceivers do not keep the same chip latency after each power-up or reset, as there is no deterministic phase relationship between the transmitted and received clocks after each power-up. In this paper, we propose a fixed-latency serial link based on high-speed transceivers embedded in Xilinx field programmable gate arrays (FPGAs). First, we modify the configuration and clock distribution of the transceiver to eliminate the phase difference between the clock domains in the transmitter/receiver. Second, we use the internal alignment circuit of the transceiver and a digital clock manager (DCM)/phase-locked loop (PLL) based clock generator to eliminate the phase difference between the clock domains in the transmitter and receiver. The test results of the link latency are shown. Compared with existing solutions, our design not only implements fixed chip latency, but also reduces the average system lock time.
其他摘要	High-speed, fixed-latency serial links find application in distributed data acquisition and control systems, such as the timing trigger and control (TTC) system for high energy physics experiments. However, most high-speed serial transceivers do not keep the same chip latency after each power-up or reset, as there is no deterministic phase relationship between the transmitted and received clocks after each power-up. In this paper, we propose a fixed-latency serial link based on high-speed transceivers embedded in Xilinx field programmable gate arrays (FPGAs). First, we modify the configuration and clock distribution of the transceiver to eliminate the phase difference between the clock domains in the transmitter/receiver. Second, we use the internal alignment circuit of the transceiver and a digital clock manager (DCM)/phase-locked loop (PLL) based clock generator to eliminate the phase difference between the clock domains in the transmitter and receiver. The test results of the link latency are shown. Compared with existing solutions, our design not only implements fixed chip latency, but also reduces the average system lock time.
关键词	Data acquisition circuit Fixed-latency Field programmable gate array (FPGA) Serial link Trigger system
收录类别	CSCD
语种	英语
资助项目	[National Science and Technology Support Program of China] ; [Fundamental Research Funds for the Central Universities, China] ; [Specialized Research Fund for the Doctoral Program of Higher Education, China] ; [National Science Foundation for Post-doctoral Scientists of China]
CSCD记录号	CSCD:5070737
引用统计
文献类型	期刊论文
条目标识符	http://ir.imr.ac.cn/handle/321006/152864
专题	中国科学院金属研究所
作者单位	1.中国科学院金属研究所 2.浙江大学
推荐引用方式 GB/T 7714	Liu Xue,Deng Qingxu,Hou Boning,et al. High-speed, fixed-latency serial links with Xilinx FPGAs[J]. JOURNAL OF ZHEJIANG UNIVERSITY-SCIENCE C-COMPUTERS & ELECTRONICS,2014,15(2):153-160.
APA	Liu Xue,Deng Qingxu,Hou Boning,&Wang Zeke.(2014).High-speed, fixed-latency serial links with Xilinx FPGAs.JOURNAL OF ZHEJIANG UNIVERSITY-SCIENCE C-COMPUTERS & ELECTRONICS,15(2),153-160.
MLA	Liu Xue,et al."High-speed, fixed-latency serial links with Xilinx FPGAs".JOURNAL OF ZHEJIANG UNIVERSITY-SCIENCE C-COMPUTERS & ELECTRONICS 15.2(2014):153-160.